Innovations in dynamic switch power testing

How Cosmic is redefining reliability testing for wide-bandgap semiconductor devices at production scale.

BY ROBERT PULMAN, PRODUCT MANAGER - HIGH POWER TEST COSMIC GROUP

The electrification of mobility and the rapid proliferation of industrial power conversion is placing unprecedented demands on power semiconductor devices. Silicon Carbide (SiC) MOSFETs and Gallium Nitride (GaN) transistors have emerged as the materials of choice for next-generation power electronics thanks to their ability to switch at higher frequencies, block higher voltages and operate at elevated temperatures compared to conventional silicon. But these performance advantages come with a critical manufacturing challenge: how to verify devices as truly reliable before they reach their end applications? The answer lies in dynamic switch power testing — a discipline that has evolved dramatically in recent years to keep pace with the technical complexity of wide-bandgap (WBG) devices and the tightening requirements of automotive and industrial qualification standards. Cosmic Group, a global partner in advanced semiconductor test solutions, has been at the forefront of this evolution, developing a portfolio of test platforms that bring production-grade dynamic testing to every stage of the device lifecycle from bare dies to packaged module.

Why power device testing cannot be static
Traditional parametric testing — measuring static electrical parameters such as on-resistance, threshold voltage, and leakage current — remains essential, but it captures only a snapshot of a device’s behaviour under controlled, steady-state conditions. In real-world applications, power devices are subjected to continuous high-frequency switching, large transient currents, and extreme thermal cycling. Static tests alone cannot reveal how a device will behave under these conditions, nor can they expose latent defects that only manifest under dynamic stress.

Cosmic DS5-400 Adapter

There are four primary motivations for dynamic power device testing, each addressing a distinct aspect of device integrity:

• Doping and crystal quality — Verifying wafer quality at the material level to ensure defect-free crystal structure
• Stress testing — Driving devices harder than real-world conditions to expose early-life failures
• Gate oxide layer quality — Assessing the integrity of the gate dielectric, which is especially critical in SiC devices
• Die sorting — Categorising Known Good Die (KGD) parameters to ensure matched performance across dies in multi-die modules

The third and fourth points deserve particular attention for SiC technology. SiC MOSFETs rely on an extremely thin gate oxide layer —the SiO₂ dielectric interface between the Gate and the conduction channel — that is inherently more vulnerable to time-dependent dielectric breakdown (TDDB) than equivalent silicon devices. Carbon migration from the SiC substrate into the oxide layer can cause charge trapping, which shifts threshold voltages and degrades switching performance over time. As voltage ratings climb beyond 1.7 kV in emerging applications, and as switching speeds increase with the adoption of low-inductance packaging techniques, the risks associated with gate oxide integrity become even more pronounced. Dynamic testing is the only way to stress these mechanisms under conditions that replicate actual operation.

The regulatory imperative: AQG324 and evolving automotive standards
The Automotive industry has long operated rigorous qualification frameworks, and industrial power electronics are no exception. The AQG324 standard defines a comprehensive suite of qualification tests, including power cycling HTS, LTS, HTRB, HTGB and H3TRB.

Critically, AQG324 mandates dynamic testing as part of the reliability assessment process. Two tests in particular — Dynamic Reverse Bias (DRB) and Dynamic Gate Stress (DGS) — are required for technology qualification, with a minimum of 10¹¹ cycles. While this cycle count may seem excessive for production testing, truncated versions of these tests, typically 10k to 100k cycles, are being increasingly requested at final test. At a switching frequency of 1 MHz, a 10k-cycle DRB test completes in just 10 ms — a negligible impact on overall test throughput, especially when index-parallel test configurations are employed. This evolution in standards reflects a broader industry consensus: that WBG devices intended for safety-critical automotive applications cannot be adequately qualified through static testing alone.

Short-Circuit testing: surviving the worst case
One of the most demanding tests in the dynamic testing toolkit is the Short-Circuit Test (SCT). In synchronous motor drive applications, power devices are invariably arranged as three half-bridge configurations. If both upper and lower devices in a bridge leg turn on simultaneously — called “shoot-through” — the result is a direct short-circuit across the battery or DC bus. The power devices must survive long enough for the motor drive protection circuitry to detect the fault, disconnect the energy source and prevent catastrophic damage to the system.

During a short-circuit event the current through the device is limited only by its RDS(on) resistance and the stray inductance of the circuit. For a high-current SiC device, this can mean short-circuit currents reaching up to 10x the normal operating current — a brutal stress test by any measure. SiC devices also exhibit fundamentally different failure mechanisms compared to silicon under high-stress conditions, which makes the SCT an essential part of building a complete picture of device behaviour in production, not just in qualification laboratories.

The critical role of inductance
Implementing SCT in production is not trivial. The test requires a high-energy DC source, fast gate drive circuitry for the device under test (DUT), accurate current and voltage measurement and robust fault-condition protection. But one factor above all others determines the quality and repeatability of the test: stray inductance in the test circuit.

By way of example, measurements on a SiC TO247-4 device with a datasheet short-circuit current of 1,800A at 470V illustrate the impact dramatically: With a 20cm cable connection (~200nH) and a Vds of 100V, the peak current only reaches about 1,000A and the overshoot voltage peaks at 470V. A hard-dock connection (~40nH) on the other hand achieves a peak current of 1,500A and peak Vds of a much more controlled 245V (see adjacent graph.)

Cosmic 0cm waveform.

The conclusion is unambiguous: reducing inductancein the test path is not a refinement but fundamental requirement for obtaining meaningful SCT results. A hard-dock connection to the DUT, minimising the length of the switching loop, is the preferred approach in production test systems designed for this purpose.

Dynamic Reverse Bias testing: Stressing the gate oxide
Where SCT probes the device’s ability to survive extreme overcurrent conditions, the Dynamic Reverse Bias (DRB) test targets a different vulnerability: the integrity of the device under repeated high-voltage transient stress. The DRB test applies repeated high-voltage spikes to the drain of the DUT while it is held in the off-state, creating fast charge and discharge cycles through the internal structure of the die. This cycling is specifically designed to expose premature aging mechanisms including charge trapping at the SiC/SiO₂ interface, dielectric breakdown in the gate oxide and degradation of the body diode. AQG324 specifies a minimum slew rate of 50 V/ns for the drain voltage transient, but in practice, with careful attention to reducing the capacitance of the circuit path between the tester and the device handler, slew rates of 100 V/ns and above are achievable and preferable — offering accelerated exposure of latent defects.

A practical DRB test example using a high voltage SiC MOSFET demonstrates the key parameters in action: a switching frequency of 500 kHz and dv/dt of 96V/ns is achievable in production with optimised gate drive conditions. Factors govern the achievable slew rate: the choice of upper switching device and overall capacitance of the drain-source loop, the switching speed of the upper device gate driver, loop inductance, stability of the DUT gate-source voltage and bandwidth of the measurement system.

KGD Testing: protecting module economics
As SiC power modules for automotive applications become increasingly sophisticated — integrating multiple dies in half-bridge and full-bridge configurations — the economics of die-level testing have become compelling. A typical mid-volume automotive-grade 1,200 V SiC half-bridge module has a cost structure in which the individual dies account for approximately 55% of total cost, the substrate for 15%, and final module assembly for the remaining 30%.

Even for the simplest full-bridge module incorporating just 6 dies, the arithmetic is stark: if just one die is defective and the fault is not detected until after module assembly, 93% of total module cost has already been committed. This makes KGD testing a critical process step, not merely a quality assurance formality. Beyond defect screening, parametric KGD testing also enables die-to-die matching, ensuring that all elements of a finished module switch in harmony and share the load symmetrically.

To achieve a module yield of at least 85%, the required average die yield is 99.55%, assuming a defect-free assembly process — a target that demands extremely sensitive and reliable die-level test methods.

Cosmic DS6

Safety in dynamic testing: protecting the test socket
High-power dynamic testing at die level introduces further challenge that is often underappreciated: what happens when device fails during the test itself? Dynamic switch test involves high currents and voltages; if the DUT fails destructively, the energy dissipated in the device and through the test fixture can be sufficient to damage not only the socket but also the mechanical handling components.

Effective over-current protection must accomplish three things simultaneously: distinguish a fault event from a normal test transient, limit the energy delivered to the DUT during reaction window and disconnect energy sources as rapidly as possible. In a well-designed system, shutdown can be achieved in under 300 ns from fault detection — a response time that makes difference between a recoverable failure and catastrophe. Cosmic’s SocketSafe™ technology, integrated into its higher-end platforms, provides this level of protection for both KGD and packaged device test sockets, reducing cost and downtime.

Cosmic Group’s Dynamic Switch test portfolio
Cosmic’s Dynamic Switch product family addresses the full spectrum of test requirements from entry-level GaN device characterisation to ultra-high-power SiC automotive module testing. The portfolio currently comprises three platforms:

The DS5-400 is designed for packaged devices and supports single-, double- and multi-pulse test modes, making it well suited for GaN characterisation where high switching speed is the primary concern. DS5-QUASAR and DS6-PULSAR extend the capability to die-level testing and incorporate SocketSafe™ over-current protection, with PULSAR supporting short-circuit test currents up to 10,000 A for the most demanding automotive SiC qualification scenarios. All 3 platforms are designed around an H-bridge configuration that enables SCT, DRB and inductive load tests within a single flexible test platform.

Crucially, the same test platforms used for laboratory research and characterisation scale seamlessly to high-volume production. This continuity — from first characterisation through to volume manufacturing — ensures that test conditions applied during device qualification are faithfully replicated at production speed, eliminating the risk of systematic differences between qualification data and real-world production performance.

A new standard for power device reliability
The message from the semiconductor test community is clear: as WBG power devices move from niche applications into mass-market automotive and industrial power conversion at scale, the test strategies developed for conventional silicon are no longer sufficient. Dynamic switch testing — encompassing short-circuit testing, dynamic reverse bias testing, and KGD evaluation — is not a premium option reserved for research labs. It is a production necessity.

Cosmic Group’s investment in this area, backed by the combined expertise of Test Inspire, Gedec, RoodMicrotec, ipTEST, Microtest and Focused Test, represents our commitment to the industry’s most pressing reliability challenges.

Cosmic Quasar

With over 25 years of accumulated test expertise and a global footprint spanning Europe, the US, and Asia, the group is uniquely positioned to support device manufacturers as they navigate the transition to the next generation of power semiconductors — and to the test infrastructure that will underpin their success.