How to pick a hot-swap MOSFET

A comprehensive guide on how to select MOSFETs for server applications and how to evaluate their suitability for hot-swap operation.

By Nexperia

Hot-swap application overview
Hot-swap circuits are found in applications where a subsystem can be removed without disturbing or powering down the rest of the system. In the case of computing and data management, such as AI servers; individual trays of GPUs, CPUs, or network switches cannot disturb the rest of the server rack within the data center. This makes AI servers an excellent candidate for hot-swap circuits.

As a result, hot-swap circuits require in-rush current control, fault protection, and controlled turn on-and turn-off functions as they pass power from a centralized source (i.e. 48 V busbar) to a subsystem (i.e. individual server trays). The MOSFET pass element (Q1 in Fig. 1 IC (Hot-swap Controller in Fig. 1 ) and controller ) are separated because of high power requirements. As a result, certain MOSFET parameters must be considered.

Maximum drain-to-source voltage (VDSmax), drain-to-source on-state resistance (RDSon), packaging, paralleling technology, and Safe Operating Area (SOA) will be discussed in detail to simplify the MOSFET selection process. In addition, this will explain why Nexperia’s enhanced SOA hot-swap MOSFETs , such as the PSMN2R3-100SSE , excel in the market.

Figure 1. Hot-swap block diagram.

MOSFET parameters for standard operation
Input voltage (VIN_typ) vs. maximum breakdown voltage (VDSmax) For newer and modern data center architectures, the busbar voltage, or input voltage (VIN_typ) to an individual server tray, is within a range of 40 V – 60 V. The typical value of the input voltage will either be 48 V, 50 V, or 54 V. However, transient voltage surges or spikes, in combination with system parasitics (i.e. busbar and wires from the rack to the power distribution board), will induce voltage much higher than the typical range and destroy the MOSFET if the maximum breakdown voltage (VDSmax) is exceeded.

As a result, most designers have determined that VDSmax is 100 V for 54 V systems. More information can be found in the Calculating V DSmax of a MOSFET section.

Because VDSmax determines packaging, RDSon range, and ultimately price of the MOSFET, it is important to pick the VDSmax first. In any case, Nexperia offers enhanced SOA hot-swap MOSFETs with VDSmax at both 80 V and 100 V, such as the PSMN2R3-100 SSE.

Input power and current vs. MOSFET power dissipation (RDSon)
Input power (PIN_typ) is the wattage requirement determined by the circuits within a subsystem. In the case of server trays, GPUs and CPUs will determine most of the power, which ranges from 1.2 kW – 2.2 kW in current architectures and 2 kW – 4 kW in near-future architectures.

Equation 1 Where: determines the typical input current (IIN):

Figure 2. Power Density - Max Power Dissipation vs. Horizontal Length Target (TJ = 113 °C, TA = 50 °C).

• IIN is the input current seen by the system [A]
• PIN_typ is the typical input power seen by the system [W]
• VIN_typ is the typical input voltage seen by the system [V]

Equation 1 (Equation 1) yields a range of 22 A – 74 A, which are typical input currents in modern server architectures. This ultimately leads to power dissipation (PD) in the MOSFET, which is the limiting factor in most MOSFET circuits.

While the maximum junction (or die) temperature rating of Nexperia hot-swap MOSFETs is 175 °C, most designers will have a target junction temperature (TJ_target) and other system requirements that they must adhere to.

Typical target junction temperatures can range from 100 °C – 125 °C to allow for transient events, and ambient temperatures can range from 50 °C – 85 °C depending on cooling paths within the server tray. Thermal resistance (RthJA) is determined by the MOSFET package and layout, which is discussed in more detail in MOSFET Packages and Paralleling with Application Specific (ASFET) technology section, but an 8x8 mm MOSFET with good layout is used for this example.

In combination with the calculated input current (74 A), 0.328 mΩ is calculated in the Calculating target RDSon of a singular MOSFET section. However, there are no 0.328 mΩ MOSFETs available on the market. As a result, designers will place several MOSFETs in parallel to achieve higher current capability.

MOSFET packages and paralleling with ASFET technology
Fig. 2 shows a graph of popular hot-swap MOSFET’s, including PSMN2R3-100SSE, maximum server tray power vs. horizontal PCB area. This determines how many MOSFETs in parallel are needed for a system’s target power.

To achieve the target input current of 74 A (or 4 kW), Fig. 2 indicates that several parallel MOSFETs (e.g. 4) can be used. This is determined by Equation 2:

Where:

• TJ_target is the target junction or die temperature [°C] (Equation 2)
• RthJA is the thermal resistance from junction to ambient, which usually consists of PCB and MOSFET package thermal resistance [°C/W or K/W]
• Tamb is ambient temperature of the system [°C]
• IIN is the input current seen by the system [A]
• RDSon@temp is the maximum RDSon adjusted from 25 °C to the target temperature using the data sheet [Ω]
• nparallel is the number of MOSFETs in parallel

As discussed in “LFPAK MOSFET thermal design guide How to pick a hot-swap MOSFET ” application note, package construction and dimensions play a large role in determining thermal impedance or thermal capability of a MOSFET. Both the PSMN2R3-100SSE (LFPAK88, SOT1235, 8x8mm) and PSMN1R0-100ASE (CCPAK, SOT8000A, 12x12mm), benefit from copper clip technology for the best thermal performance, as opposed to bond wires used in TOLL (e.g. PG-HSOF-8-1, 10x12mm). This performance improvement will be reflected in a MOSFET’s Safe Operating Area (SOA) graph, and thermal package impedance graph located in the data sheet.

Figure 3. ID vs VGS for regular and ASFET technology to improve paralleling.

While packaging is important, PCB layout is a main contributor to the thermal path (i.e. 0.44 °C/ W for the thermal impedance of package vs. approximately 35 °C/W for the thermal impedance of the PCB). Ideal and realistic PCB thermal resistances (RthJA), such as 35 °C/W for LFPAK88, can be found in the “Thermal boundary condition study on MOSFET packages and PCB substrates ” application note.

The PSMN2R3-100SSE’s maximum RDSon at 175 °C is 5.2 mΩ, which is a great choice for this application requirement of 5.259 mΩ calculated by Equation 2. This difference adds margin when comparing the actual junction temperature to the target. Note that Fig. 2 shows that the PSMN1R0-100ASE has the best power density (i.e. largest slope) out of any device in the market. The PSMN1R0-100ASE is a 1 mΩ, 12x12 mm, Enhanced SOA MOSFET using the CCPAK package. This device has a clear advantage and gives the best performance, or most margin, at higher power (i.e. >5 kW designs under the same assumptions).

Figure 4. Example of unmatched MOSFET threshold voltages (VGSth) resulting in inequal input current (IIN) for Regular (right) and ASFET (left) technology.

Figure 5. Hot-swap simulation and typical waveforms.

As discussed in “Paralleling power MOSFETs in high power applications ” application note, mismatch in gate-source threshold voltage (VGSth), sometimes called the MOSFET “on” voltage, will lead to uneven current sharing between MOSFETs that would result in higher input current (IIN) for a singular MOSFET as shown in Fig. 4.

Fig. 3 shows 3 types of MOSFET technology: Regular technology (PSMN2R0-100SSF), Application Specific MOSFET (ASFET) technology with enhanced SOA (PSMN2R3-100SSE), and ASFET technology with enhanced current sharing (PSMN2R3-100SSJ). Choosing enhanced SOA ASFET family will result in 2 to 4 times better current sharing for worst case VGSth separation compared to Regular technology. This is also demonstrated in the waveforms shown in Fig. 4.

As a result, choosing a MOSFET in the enhanced SOA ASFET family, such as PSMN2R3 100SSE, will benefit from the enhanced current sharing.

MOSFET parameters during hot-swap operation
As seen in Fig. 5, typical hot-swap controllers will linearly and constantly charge the gate of the MOSFET to facilitate a controlled turn-on. This operation puts the MOSFET into current source mode, sometimes called linear mode, which constantly charges the bulk capacitance (Vout). The MOSFET current source mode is extensively discussed in the “Power MOSFETs in linear mode” application note, and one of the most stressful modes a MOSFET can operate in.

As a result, there are 4 important aspects for linear mode operation:

• Voltage at the input to be transferred to the output (VIN or VD)
• In-rush current needed to charge the bulk capacitance (IINRush)
• The amount of time taken to charge the bulk capacitance (tpulse)
• Pulse Shapes of current and voltage or energy (triangular or rectangular)

Input voltage (VIN) is the same as the system’s input voltage, so 54 V is used.

Figure 6. Safe Operating Area (SOA) comparison between Regular and ASFET technology.

Figure 7. Example start-up into short circuit waveforms using ADI’s LTC4238 hot-swap controllers.

The VDS voltage pulse shape is triangular, and the current pulse is rectangular, which results in a triangular power pulse shape as shown in Fig. 5 . This effectively doubles the SOA performance of the MOFSET as discussed in “Power MOSFETs in linear mode ” application note.

The amount of time (tpulse) and the in-rush current (IINRush) depend on bulk capacitance, the input voltage (VIN), the hot-swap controller’s gate voltage slew rate or source current, and fault conditions. For most hot-swap server applications, this time is between 800 μs – 500 ms. In modern architecture, 10 ms or 100 ms are the typical benchmarks.

Ultimately, these values are compared against the MOSFET’s Safe Operating Area (SOA) graph in the data sheet, as shown in the Safe Operating Area (SOA) of a MOSFET and ASFET technology section.

Due to the complex interaction between MOSFET, Hot-swap Controller, and bulk capacitance; simulation is the recommended way to establish a baseline before the prototyping phase. Refer to Fig. 5 and “Nexperia Precision Electrothermal models in SPICE and VHDL-AMS for Power MOSFETs” application note. Otherwise, the Imprecise calculation of hot-swap pulse time will help for generic calculations.

Figure 8. Common hot-swap faults in context of Safe Operating Area (SOA.

Safe Operating Area (SOA) of a MOSFET and ASFET technology
Safe Operating Area (SOA), as shown in Fig. 6, illustrates the range of voltage, current, and pulse length where operating below the lines will indicate safe operation.

For power MOSFETs in linear mode there is a significant reduction in performance, which can be reviewed in the Definition of Safe Operating Area (SOA) regions and Spirito effect section. This phenomenon is known as the Spirito effect, and MOSFETs with Enhanced SOA ASFET technology eliminate the Spirito effect which increases SOA performance and margin as shown in Fig. 6.

Comparing the example in Fig. 6 where VIN is 54 V, the pulse shape is triangular, tpulse is 100 ms, and the MOSFET is the PSMN2R3-100SSE; the SOA current results in 14 A (or 2 multiplied by 7) at TJ = 25 °C for, which is approximately 4 times better performance compared to the PSMN2R0-100SSF, non-enhanced SOA MOSFET (3.5 A or 2 multiplied 1.75).

As shown in the Imprecise calculation of hot-swap pulse time section example, the regulated in rush current is around 8 A and 54 V, for 120 mF and approximately 100ms, which is below the 14 A limit at 100 ms for the PSMN2R3-100SSE.

Recalculating SOA performance for different tpulses, shapes, and temperatures is discussed in “Power MOSFETs in linear mode ” application note and Example of re-rating SOA graph for temperature section.

Fault conditions such as start up into short circuit
There are many fault conditions that can occur to a MOSFET in a hot-swap application. The most demanding fault is start-up into short circuit as shown in Fig. 7.

Start-up into short circuit shows that the VDS and current are both large which result in a larger instantaneous power compared to a running short-circuit, where VDS is small but current is large. This is shown on the right side of Fig. 8. In some cases, this energy is more than the energy seen during a normal hot-swap operation to charge the bulk capacitors.

As a result, it is important to compare the VIN, IINRush, tpulse, and shape during this fault condition to the SOA graph in data sheet.

The role of hot-swap controllers during fault conditions
Ultimately, the resulting waveform during a fault condition is the combination of parasitics in the system and the hot-swap controller’s reaction. If a MOSFET passes every use-case except a fault, changing the MOSFET might not be the solution or an option without a redesign.

Luckily, the best hot-swap controllers, such as Texas Instrument’s LM506x series and Analog Devices LTC42xx series, are configurable using software which can help reduce stress on the MOSFET without redesigning.

For example, the current is detected through the shunt resistor and the sensing pins of the hot-swap controller as shown in Fig. 1. Fault detection time and deglitch filters of the hot-swap controller will determine when the fault triggers, which should help determine worst case tpulse. Both LM506x and LTC42xx can adjust or shorten these fault timers.

As a result, always consider the role of the hot-swap controller and how it can reduce energy exposed to the MOSFET.

Conclusion
Hot-swap circuits are found in AI server applications because of the relationship between the rack’s busbar and the server tray. Hot-swap circuits require features, such as in-rush current control, fault protection, and controlled turn on and turn off that will stress the MOSFET. Key parameters such as maximum drain-to-source voltage (VDSmax), drain-to-source on-state resistance (RDSon), packaging, paralleling technology, and Safe Operating Area (SOA) must be considered in the MOSFET selection process.

Notably, Nexperia’s enhanced SOA hot-swap ASFET MOSFETs , such as the PSMN2R3-100SSE , are perfect for modern and near future server hot-swap designs.